Many conventional microprocessors use ‘pipelines’ to increase parallelism and performance. That is, where instruction execution in a microprocessor comprises several independent steps, separate units can be created in the microprocessor to carry out each step. When a unit finishes executing an instruction, it is passed on to the next unit in the ‘pipeline’, and starts work on the next instruction. Therefore, although the length of time required for an entire instruction to be executed remains the same as in a non-pipelined system, as the next instruction is only one unit behind, the overall result is that the performance of the microprocessor is improved.
In asynchronous processors, the pipeline stages are generally implemented using latches. In order to allow asynchronous microprocessors to be tested, a second layer of latches is often added to each pipeline stage. These latches combine with the original latches to create master-slave pairs. The master-slave pairs can then be clocked alternately to test the microprocessor circuitry. However, the additional layer of latches needed to create the master-slave pairs increases the silicon area required to implement the microprocessor design. Furthermore, the latches that are added are often scannable latches, which allow values to be scanned in for testing purposes. These scannable latches require more silicon area than normal latches.
Another disadvantage of adding an extra layer of latches is that when the microprocessor is not running in a test mode, the data still has to go through both of the latches in each stage, thus increasing the latency of the data path and the power consumption of the processor.
One way to circumvent the use of an additional layer of latches is to use a latch of one pipeline stage in combination with the latch in the next stage to create the required master-slave pairs. However, at the time of the invention, there is no automated way to achieve this, and designers have to manually examine the design to determine which latches to combine. Furthermore, in many instances this method cannot be used, and the designer is still forced to add an additional layer of latches to allow the processor to be tested.
There is therefore a need for a testable latch-based microprocessor that overcomes these disadvantages.